Title: Enabling FPGA Accelerators Using the Acceleration Stack for Intel® Xeon® CPU with FPGAs

The Acceleration Stack for Intel® Xeon® CPU with FPGAs is a robust collection of software, firmware, tools and hardware intended to make it easier to develop and deploy Intel FPGAs for workload optimization in data center and cloud environments. In this training, we will discuss and practice how software developers can write host code that can communicate with the FPGA accelerator transparently using the Open Programmable Acceleration Engine (OPAE) and walkthrough how FPGA and accelerator developers can build, test and integrate their Accelerator Functional Units (AFUs) into the FPGA.


June 5, 13:30-18:00


  • Introduction and acceleration stack overview
  • Getting Started with the Acceleration Stack
  • Developing a SW host application
    • Lab1
  • Introduction to Accelerator Functional Unit (AFU)
  • Creating an Accelerator Functional Unit (AFU)
  • Co-simulation using AFU Simulation Environment (ASE)
  • Compiling the Accelerator Function Unit into an Accelerator Function (AF)
  • Debugging an Accelerator Function
    • Lab 2
  • Getting Started
    • Lab 3
Note: Bring your own windows or MAC laptop to the workshop
Note: If the number of applicant exceeds the capacity, further application will not be accepted.

Please send an email to yukitaka.takemura@intel.com with the following items.

  • Email subject: Workshop at HEART2019
  • Attendee”Ēs name
  • All attendee”Ēs email addresse
  • Organization(company/university/college and department) name
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