Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation (bibtex)
by K. Dohi, Y. Yorita, Y. Shibata, K. Oguri
Reference:
Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation (K. Dohi, Y. Yorita, Y. Shibata, K. Oguri), In Field Programmable Logic and Applications (FPL), 2011 International Conference on, 2011.
Bibtex Entry:
@INPROCEEDINGS{dohi:2011:fpl, 
author={Dohi, K. and Yorita, Y. and Shibata, Y. and Oguri, K.}, 
booktitle={Field Programmable Logic and Applications (FPL), 2011 International Conference on}, 
title={Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation}, 
year={2011}, 
pages={478-481}, 
keywords={augmented reality;data compression;edge detection;field programmable gate arrays;image coding;image matching;learning (artificial intelligence);Virtex-5 FPGA;augmented reality;combinational circuit;corner pattern compression method;corner pattern matching;discriminant division;features from accelerated segment test corner detection;machine learning;parallel mapping;parallel tracking;pattern symmetry;stream-oriented FPGA implementation;Detection algorithms;Equations;Feature extraction;Field programmable gate arrays;Hardware;Image coding;Random access memory;FAST corner detection;Logic compression}, 
doi={10.1109/FPL.2011.94},}
Powered by bibtexbrowser